ds2291 t1 long loop stik ds2291 * service mark of at&t communications 022798 1/10 features ? recovers clock and data off of t1 lines from 0 to 6,000 feet in length ? +0 to -30dbsx receiver sensitivity ? built-in automatic line build out (albo) circuitry; no tuning or external components required ? dejitters the recovered clock and data ? meets tr 62411 (dec. 1990) for jitter tolerance and attenuation ? companion to the ds2290 t1 isolation stik ? connects to a standard 30-pin single in-line connector ? single +5v supply ? compatible with the ds2180a or ds2141a t1 trans- ceivers descriptionthe ds2291 t1 long loop stik contains all the circuitry necessary to recover clock and data from a t1 line. the ds2291 contains an automatic line build out (albo) circuit that allows it to adapt to t1 lines varying in length from 0 to 6,000 feet. it also will dejitter the recovered clock and data according to the jitter attenuation curves outlined in at&t communications document tr 62411 (accunet* t1.5 service description and interface speci- fication - december 1990). applications area include channel service units (csu), t1 monitoring equip- ment, and t1 test equipment. pin assignment vdd 1 b8zs 20 gnd 23 vdd 2 lb 9 nc 10 gnd 22 rclk 3 rpos 4 rneg 5 lpos 7 lneg 8 nc 11 rcl 14 nc 13 bpv 15 rx 30 rx+ 29 nc 28 nc 27 nc 26 nc 25 dja 19 nc 18 lock 16 nc 12 lclk 6 bl 17 nc 24 dejitter circuitry albo & clock recovery circuitry (actual size) rst 21 overview the ds2291 contains onboard albo circuitry that al- lows it to recover clock and data from t1 lines up to 6,000 feet in length. (see figure 1.) unlike alternative methods of clock and data recovery from t1 lines, the ds2291 does not require any tuning, nor does it need any additional external circuitry. the state of the lock pin indicates whether the ds2291 has been able to phase and frequency lock to the incoming t1 signal. if the lock pin is high, the ds2291 is properly locked onto the incoming signal. the ds2291 meets the latest t1 specification for jitter tolerance. the jitter tolerance curve in figure 2 is applicable over the full dynamic in- put range of the ds2291. downloaded from: http:///
ds2291 022798 2/10 once the long loop stik has recovered data from thet1 line, it can decode b8zs code words and check for bipolar violations and carrier loss. if the b8zs pin is tied high, the ds2291 will automatically replace incoming b8zs code words with eight zeros. if the b8zs pin is tied low or left open, no replacement occurs. bipolar viola- tions are reported via the bpv pin. the bpv pin will tran- sition high for a full t1 bit period (648 ns) each time a vio- lation is detected. bipolar violations inherent in b8zs code words are not reported if the b8zs pin is tied high. the ds2291 also checks for carrier loss. the rcl pin will transition high when the ds2291 detects 192 con- secutive zeros at rx+ and rx-. the recovered clock and data are passed to the dejitter circuitry. if the dja is tied low or left open, the ds2291 will attenuate the jitter present at rx+ and rx- accord- ing to the curves outlined in figure 3. these curves meet the latest t1 specifications. if the dja pin is tied high, the ds2291 will not attenuate jitter. hence, all the jitter inherent in the signal at rx+ and rx- will be passed to rclk, rpos, and rneg. if the recovered clock at rclk is used to transmit data onto t1 lines, it is recom- mended that the dejitter circuitry be enabled (dja = 0). the dejitter circuitry contains a 128-bit buffer. this buffer can be recentered on command via the rst pin. in nor- mal applications, the rst is left open or tied high. the buffer limit (bl) output will transition high when the ds2291 is receiving more than 120 unit intervals peak-to-peak (ulpp) of jitter at rx+ and rx-. as long as the incoming jitter is less than 120ulpp, the bl pin will remain low. the ds2291 contains a data mux that allows data to be routed from either the t1 recovery circuitry or from a lo- cal source. the mux is helpful locating faults in a sys- tem. for example, it could be used to implement a alocalo loopback. two typical applications with the ds2291 are shown in figure 4 and figure 5. in both applications, the ds2291 is used to recover data from t1 lines up to 6,000 feet in length. the application in figure 4 is with an unpro- tected interface; it might be used in t1 test equipment. the application in figure 5 is with the ds2290 t1 isola- tion stik, which provides all the necessary protection as required by fcc part 68. this could be used in a chan- nel service unit (csu) or in similar types of equipment in which full surge and isolation protection is required. single in-line connector the ds2291 is designed to connect directly into a 30-pin single in-line connector. these connectors are available from a number of vendors. downloaded from: http:///
ds2291 022798 3/10 pin description table 1 pin symbol i/o description 1,2 v dd - positive supply. 5.0 volts. 3 rclk o receive clock. recovered 1.544 mhz clock. 45 rpos rneg o receive bipolar data. recovered bipolar data; updated on the rising edge of rclk. bipolar violations are not corrected. 6 lclk i loopback clock. clock for loopback data. internally pulled low by 100k ohm. 78 lpos lneg i loopback bipolar data. samples on the falling edge of lclk if lb is tied high. internally pulled low by 100k ohm. 9 lb i loopback enable. tie high to loopback data from the lpos and lneg inputs to rpos and rneg; tie low or leave open toobtain recovered data out of the albo circuitry at rpos and rneg. internally pulled low by 100k ohm. 14 rcl o receive carrier loss . transitions high when 192 consecutive zeros have been received at rx+ and rx-; reset on the nextones occurrence. 15 bpv o receive bipolar violation. transitions high for a full bit period when a bipolar violation appears at rx+ and rx-. b8zs codewords are not reported if b8zs is tied high. 16 lock o lock indication . high state indicates that the recovery circuit is phase-and frequency-locked to the signal at rx+ and rx-. 17 bl o buffer limit. transitions high when the incoming jitter at rx+ and rx- is greater than 120ulpp. 19 dja i disable jitter attenuation. tie high to disable the jitter attenu- ation circuitry; tie low to enable the jitter attenuation circuitry. internally pulled low by 100k ohm. 20 b8zs i b8zs enable. if tied high, incoming b8zs code words are de- coded and replaced with eight zeros. if tied low, b8zs code words are not decoded. internally pulled low by 100k ohm. 21 rst i reset. active low; a high-low-high transition will recenter the dejitter buffer. internally pulled high by 100k ohm. 22, 23 gnd - ground. 0.0 volts. 2930 rx+ rx- i o receive analog inpu t. connects to t1 line through a 2:1 trans- former. see figure 4. note: do not connect any signal to pins 10, 11, 12, 13, 18, 24, 25, 26, 27, or 28. downloaded from: http:///
ds2291 022798 4/10 ds2291 block diagram figure 1 rst(21) pd pd pu pdpd pd pd lock(16)rcl(14) bpv(15) b8zs(20) vdd(1,2) gnd(22,23)rclk(3) rpos(4) rneg(5) dja(19) bl(17) dejitter circuitry data mux carrier loss/ bpv detect/ b8zs decode clock & data automatic line build out rx+(29) rx-(30) lclk(6) lpos(7) lneg(8) lb(9) recovery downloaded from: http:///
ds2291 022798 5/10 ds2291 jitter tolerance figure 2 frequency (hz) 1k 100 10 1 0.1 10 100 1k 10k 100k tr 62411 nominalds2291 performance unit intervals (ulpp) ds2291 jitter attenuation performance figure 3 frequency (hz) 1 10 100 1k 10k 20 hz nominal ds2291 performance 0 2040 60 tr 62411 curve b tr 62411 curve a jitter attenuation (db) downloaded from: http:///
ds2291 022798 6/10 ds2291 application (unisolated interface) figure 4 receive t1 pair tais lb tclk tpos tneg lclk lpos lneg rx lclk lpos lneg lb rclk rpos rneg rclkrpos rneg tclk tpos tneg rser tser serial port rcl bpv lock dja pcs b8zs system controller (ds5000) ttip tring len0/1/2 3 transmit t1 pair rx+ 25 ohms 2:1 1:1.4 ds2186 transmit line interface ds2291 t1 long loop stik ds2180a t1 transceiver system backplane rst 0.47 m f nonpolarized ds2291 application (isolated interface) figure 5 ds2250 microcontroller stik rxtiprxring lpwr+ lpwr receive t1 pair transmit t1 pair lb0lb1 tais lb tclk tpos tneg lclk lpos lneg rx+ rx rx+rx lclk lpos lneg lb rclk rpos rneg rclkrpos rneg tclk tpostneg rser tser serial port b8zs lb2 rcl bpv lock dja pcs b8zs txtiptxring ds2290 t1 isolation stik ds2291 ds2180a t1 transceiver t1 long loop stik system backplane rst downloaded from: http:///
ds2291 022798 7/10 absolute maximum ratings* voltage on any pin relative to ground 0.3v to v cc + 0.3v operating temperature 0 c to 70 c storage temperature -55 c to +125 c * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maxi- mum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 c to 70 c) parameter symbol min typ max units notes logic 1 v ih 2.0 v cc +0.3 v 3, 4 logic 0 v il -0.3 +0.8 v 3, 4 supply v dd 4.75 5.25 v capacitance (t a =25 c) parameter symbol min typ max units notes input capacitance c in 30 pf 3 output capacitance c out 50 pf 3 dc electrical characteristics (0 c to 70 c; v dd = 5v + 5%) parameter symbol min typ max units notes supply current i dd 40 50 ma 1 input leakage i i -100 +100 m a 2, 3 output current (2.4v) i oh -1.0 ma 3 output current (0.4v) i ol +4.0 ma 3 notes: 1. v dd = 5.25v; output open. 2. v ss < vin < v dd . 3. does not apply to rx+ and rx-. 4. inputs lclk, lpos, and lneg are hc inputs; v ih =3.5v and v il =1.0v. downloaded from: http:///
ds2291 022798 8/10 digital electrical characteristics (0 c to 70 c; v dd = 5v + 5%) parameter symbol min typ max units notes lpos, lneg setup to lclk fal-ling t sd 50 ns lpos, lneg hold from lclkfalling t hd 50 ns propagation delay from rclk to rpos, rneg valid t pd 50 ns rclk period t p 648 ns rclk pulse width t wl , t wh 324 ns rst pulse width t rst 1 m s analog electrical characteristics (0 c to 70 c; v dd = 5v + 5%) parameter symbol min typ max units notes input signal range v ir -30 +0 dbsx 1 input impedance at 772 khz z in 1100 ohms 1 note: 1. dbsx = 3vpk; signal defined at the primary side of a 2:1 transformer with the secondary shunted by 25 w and connected to rx+ and rx- (see figure 4 for an example). ac timing diagram figure 6 tt hd sd lclk lpos, lneg t pd t rst t tt p wh wl rclk rpos, rneg rst downloaded from: http:///
f g h c a b e d j side b side a o n p dim min max 30-pin pkg a in. b in. c in.d in. e in. f in. g in. h in. i in. 3.455 3.505 3.229 3.239 0.845 0.855 0.395 0.405 0.245 0.255 0.075 0.085 0.295 0.305 n in. o in. p in. 0.180 0.115 0.054 0.100 bsc i j in. 0.120 0.130 2.900 bsc ds2291 022798 9/10 ds2291 t1 long loop stik downloaded from: http:///
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